Einführung VERILOG

Projekt IR eines HARVARD-Mikroprozessors

             Clock, Synchronisation

Programm  <-> uP <-> Daten

            State Machine 

            Vektor Tabelle
  1. Synchronisierter Reset initialisiert State Machine
  2. StateMachine holt Reset Vektor aus Tabelle (Fix festgelegt, kann z.T. verschoben werden)
  3. Befehl an Reset Vektor kommt in Pipeline, Prefetch Register
Was ist Verilog:
VHDL vs. Verilog: verschiedene Sprachansätze:
Verilog: up to date, letzte Version von 2007, entstand aus C und VHDL, hat Funktionen, die in VHDL nicht vorhanden sind.
Schreibweise unterschiedlich, kein Deckungsgrad da Befehle unterschiedlich
Internal Error: Sub-system: AMERGE, File: /quartus/atm/amerge/amerge_kpt_op.cpp, Line: 220
cmp_merge_kpt_db
Stack Trace:
0x3DD57   : amerge_mini_merge + 0x3A977 (atm_amerge)

End-trace

Quartus II Version 9.0 Build 235 06/17/2009 SJ Web Edition
Service Pack Installed:  2
Internal Error: Sub-system: AMERGE, File: /quartus/atm/amerge/amerge_kpt_op.cpp, Line: 220
cmp_merge_kpt_db
Stack Trace:
0x3DD57   : amerge_mini_merge + 0x3A977 (atm_amerge)
0x30D5    : cfg_force_qexe_mode_off + 0x1E15 (ccl_cfg_ini)
0x3D4F2   : amerge_mini_merge + 0x3A112 (atm_amerge)
0x444DD   : amerge_mini_merge + 0x410FD (atm_amerge)

0x33F1    : amerge_mini_merge + 0x11 (atm_amerge)

0x4B0D    : MEM_SEGMENT_INTERNAL::splay_heap + 0x14D (ccl_mem)
0xA128    : mem_realloc_wrapper + 0x188 (ccl_mem)

0x94F2    : MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem)
0x2931    : RDB_WAVEFORM_OBJECT::RDB_WAVEFORM_OBJECT + 0x211 (db_rdb)
0x20A6    : QCU_ACF_SETTING::~QCU_ACF_SETTING + 0x126 (comp_qcu)
0x5A66    : QCU_ACF_SETTING::operator= + 0x3366 (comp_qcu)

0xCE32    : qexe_get_command_line + 0x3A2 (comp_qexe)
0x38E3    : QCU_ACF_SETTING::operator= + 0x11E3 (comp_qcu)
0x7C29    : QCU_FRAMEWORK::check_license + 0x139 (comp_qcu)
0xFBBD    : qexe_process_cmdline_arguments + 0x34D (comp_qexe)

End-trace

Quartus II Version 9.0 Build 235 06/17/2009 SJ Web Edition
Service Pack Installed:  2

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