MAC

Multiply and accumulate in Verilog:

Files: ex2_mac.zip

check:

AC0     15  16  1E  20
AC1     0A  0B  0F  10
T1      01  01  02  02
T1*AC0  15  16  3C  40
+AC1    1F  21  4B  10
OAC0    1F  21  4B  50

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