VHDL Demo1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Demo is
	port 
	(
		Clk			: in std_logic;
		ResetN		: in std_logic;
		TasteN1		: in std_logic;
		Led			: out std_logic_vector(7 downto 0)
	);

end entity;

architecture Demo_Arch of Demo is

type states		is(Reset, LedOnLow, LedOnHigh, LedAllOn);
signal state		: states;
signal TasteN1_old	: std_logic;	-- flipflop

-- signal counter		: std_logic_vector(31 downto 0);


begin
	-- vergleich = und nicht ==	
	-- Led <= counter(31 downto 24);

	DemoP : process(ResetN, Clk) is
	begin
		if(ResetN = '0') then
			-- setze alle LED auf 1 bei reset
			Led <= (others => '0');
			state <= Reset;
			TasteN1_old <= '1';
			
			-- counter <= (others => '0');
		elsif(Clk'event and Clk = '1') then
			-- <= ist Zuweisung!
			-- 4mal weil 4 led
			-- Led(7 downto 4) <= TasteN1 & TasteN1 & TasteN1 & TasteN1;
			-- Led(3 downto 0) <= not(TasteN1 & TasteN1 & TasteN1 & TasteN1);
			-- counter <= counter + 1;
			
			TasteN1_old <= TasteN1;

			case state is
				when Reset =>
					Led <= (others => '0');
					if(TasteN1_old = '0' and TasteN1 = '1') then
						state <= LedOnLow;
					end if;
			
				when LedOnLow =>
					Led(7 downto 4) <= (others => '0');
					Led(3 downto 0) <= (others => '1');
					if(TasteN1_old = '0' and TasteN1 = '1') then
						state <= LedOnHigh;
					end if;
					
				when LedOnHigh =>
					Led(7 downto 4) <= (others => '1');
					Led(3 downto 0) <= (others => '0');
					if(TasteN1_old = '0' and TasteN1 = '1') then
						state <= LedAllOn;
					end if;
					
				when LedAllOn =>
					Led <= (others => '1');
					if(TasteN1_old = '0' and TasteN1 = '1') then
						state <= Reset;
					end if;
					
			end case;
			
		end if;
	end process DemoP;
	


end Demo_Arch;

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